The openPOWERLINK slave stack on MAX 10 is executed in a bare metal environment on a single NIOS II softcore processor. The design uses in-built Ethernet interface on MAX 10 with the openPOWERLINK-optimized controller openMAC which enables low latency, low jitter transmission. At the same time openMAC also supports receive filters and auto response, to reduce the processor interrupt load and enable replies from the slave within an inter frame gap(IFG) latency.

 

Altera Max 10 FPGA

 

 

Hardware requirements

The hardware items required to run openPOWERLINK Hardware CN demo on MAX 10 are as follows:

  • 1 MAX 10 FPGA development board to act as the openPOWERLINK Slave
  • 1 Windows development PC
  • 1 Mini USB serial cable

 

Software requirements

Following are the software packages and its dependencies to be downloaded to run openPOWERLINK Hardware Slave demo on MAX 10:

  • Altera Quartus Prime v16.0.211 (To be installed on the development PC)

 

Build openPOWERLINK CN demo on Altera MAX 10

Following sections provide the steps to build and generate the FPGA configuration binary and NIOS II application from the source code.

  • Step 1: Build steps for the hardware design, which generates SOF and SOPCINFO file

  • Step 2: Build steps for the NIOS II application, for which the generated SOPCINFO file is required. This step generates the NIOS II BSP and the ELF file for the CN demo application

 

Step 1: Building the FPGA hardware design

This section describes the steps to build the FPGA hardware design for Max10 using the Nios II 16.0 command shell. Follow the steps below to build the hardware design and generate SOF and SOPCINFO files.

    • Open the Nios II 16.0 command shell

    • Change the directory to the MAX 10 hardware design directory inside the MAX 10 openPOWERLINK CN source code package

      • cd openPOWERLINK_V2.5/hardware/boards/altera-max10/cn-single-gpio/quartus

    • To build the hardware design, use the command

      • make all

    • It takes few minutes for the build to complete .SOF and SOPCINFO files are created in the same directory

    Building the Hardware

    Fig 1: Building the Hardware

    Hardware compilation successful

    Fig 2: Hardware compilation successful

 

Step 2: Building the CN demo application

This section describes the steps to build the CN demo application on Max10 using the Nios II 16.0 command shell. Follow the steps below to generate the demo CN application ELF file. The build steps described in this section require the SOPCINFO file to be present in the MAX 10 hardware design directory, which will be generated during the hardware design build described in the previous section.

  • Change to the openPOWERLINK embedded CN application build directory from Nios II command shell

    • cd openPOWERLINK_V2.5/apps/demo_cn_embedded/build/altera-nios2

  • Run the following command to generate the Makefile for NIOS II software build system

    • ./create-this-app

Building the Application

Fig 3: Building the Application

List of CN designs available

Fig 4: List of CN designs available

  • This will list down all Altera NIOS II based designs available in the openPOWERLINK source package. Select the number ‘1’ to choose MAX 10 CN design

Select the Altera MAX10 CN design

Fig 5: Select the Altera MAX10 CN design

 NIOS II software Makefile generation successful

Fig 6: NIOS II software Makefile generation successful

  • The previous step will generate the NIOS II software build Makefile. Once the Makefile is generated, run the following command to generate the application ELF:

    • make all

    Command to build demo CN application

    Fig 7: Select the Altera MAX10 CN design

     NIOS II software Makefile generation successful

    Fig 8: MAX 10 CN demo application compilation successful

  • It will take a few minutes for the software compilation process. After completion, the demo_cn_embedded.elf file will be generated
 

 

Run openPOWERLINK CN demo on Altera MAX 10

To run the CN demo on the Max10 FPGA Development Kit, it is required to program the FPGA configuration bitstream and the NIOS II software CN demo application on MAX 10, after the respective binaries are generated. Please follow the steps in the previous section to generate the required binaries.

Following sections provide the steps to run MAX 10 CN demo using the FPGA configuration and NIOS II application binaries generated in the previous section.

  • Step 1: Program MAX 10 with the generated FPGA configuration bit stream for openPOWERLINK CN demo

  • Step 2: Run the CN demo application binary on NIOS II

 

Step 1: Program the FPGA configuration bitstream

To download the bitstream to Max10 FPGA development board,

  • Power on the MAX 10 development board

  • Connect the Max10 board and PC via USB blaster II

  • In Nios II command shell, change to the openPOWERLINK embedded CN application build directory used in the build steps described in the previous section

  • Run the command below to download the bitstream on Max10

    • make download-bits

Configure MAX 10 FPGA

Fig 9: Configure MAX 10 FPGA

 MAX 10 configuration successful

Fig 10: MAX 10 configuration successful

 

Step 2: Run the CN demo application

  • After configuring MAX 10 with the generated FPGA bit stream (SOF) file, run the following command to download and start the CN demo application on NIOS II

    • make download-elf

Command to download the application ELF file

Fig 11: Command to download the application ELF file

 CN demo ELF download successful

Fig 12: CN demo ELF download successful

    • After the ELF download, the NIOS II automatically starts execution of the CN demo application. Now MAX 10 development board can be connected to a POWERLINK network with an MN to start operation. The user LED3 and LED4 on the development board indicate activity on the Ethernet interface.